Flash memory devices have been widely used in computer related equipment and other electronic appliances as storage devices. The nonvolatile and on-chip programmable capabilities of a flash memory are very important for storing data in many applications. As an example, flash memories are frequently used for the BIOS storage of a personal computer. In addition, the small physical size of flash memories also makes them very suitable for portable applications. Therefore, they have been used for storing programs and data for many portable electronic devices such as cellular phones, digital cameras and video game platforms.
A flash memory array circuit requires high positive or negative voltage to program and erase its memory cells. Typically, charge pump circuits are built in an integrated circuit along with a flash memory array to provide the high voltages. In order to supply high voltages and adequate current, two or three pump circuits with fairly large circuit areas are commonly included in a flash memory array circuit.
FIG. 1 shows a popular conventional charge pump circuit having eight pump stages. In the circuit structure as shown, two-phase non-overlapping pulse trains .PHI.1 and .PHI.2 are provided, for example from a pulse generator. By non-overlapping it is meant that 0 to 1, and 1 to 0 voltage transitions of one pulse never overlap with transitions of the other pulse, although duty cycle of the two pulses is not critical. As shown in FIG. 1, each waveform has a 0 to 1 voltage differential E1 that typically is equal to a power supply voltage Vdd.
The initial voltage at node A1 is Vdd-Vt, where Vt is a threshold voltage drop across M1. The rising edge of waveform .PHI.1 AC-couples through capacitor C1 to superimpose a positive transition of magnitude E1 upon the voltage at A1, raising the peak voltage at A1 to Vdd+Vdd-Vt.
Node A2 follows the potential at A1 less a threshold voltage drop Vt. Therefore, the voltage at A2 is Vdd+Vdd-Vt-Vt. However, the positive-rising transition of the .PHI.2 waveform AC-couples through capacitor C2 to initially superimpose an E1 transistion on node A2, increasing the peak voltage at node A2 to Vdd+Vdd+Vdd-Vt-Vt. Comparing the peak voltage at A2 to A1, the circuit pumps up the voltage level by a magnitude of Vdd-Vt.
Similarly, the peak voltage at each node A3, A4, . . . , A8 is also pumped up by Vdd-Vt as compared to its preceding node. As shown in FIG. 1, the eight stage charge pump circuit can output a peak voltage of Vdd+8*(Vdd-Vt) ideally. If Vdd is assumed to be 3 VDC and Vt is assumed to be 1 VDC, the output of the charge pump circuit can reach a peak voltage of 19 VDC. In practice, Vt may be much higher than 1 VDC if body effect is present. The output voltage can be much lower than 19 VDC realistically even if the device and capacitors can sustain more than 19 VDC.
The charge pump circuit as shown in FIG. 1 has a major drawback in that the capacitors in the later stages such as C5, C6, C7 and C8 must be able to withstand very high voltage to avoid being broken down if the trend of technology requires lower device breakdown voltage such as 12 VDC. Therefore, the voltage level that can be provided by the conventional pump circuit is limited by the pump capacitor junction breakdown voltage and oxide breakdown voltage.
A charge pump circuit for providing a high voltage requires many pump stages to step up the voltage level. Each stage has a pump capacitor and a diode associated with it. Therefore, to output high voltage it is necessary to fabricate the charge pump circuit and diode with thick oxide layers that are usually not desirable in manufacturing flash memory array.
The pump capacitor used in a charge pump circuit is usually constructed by connecting together the drain and source of a MOS transistor. There exists a channel turn-off problem in a MOS capacitor. When the channel is on, the full gate oxide of the transistor is used as the capacitor. However, when the channel is off, the gate is equivalently connected to two capacitors, a source which has much smaller overlap with the gate and a gate-substrate overlap capacitor. FIG. 2 illustrates an N-MOS pump capacitor that has a channel turn-off problem.
The gate-substrate overlap capacitor behaves like a parasitic capacitor connecting to ground. Therefore, the coupling ratio from the source to the gate is as low as 10%. As a result, the pump capacitor can work only when the MOS channel is turned on. The efficiency of the pump circuit is degraded.
Another issue is related to the supply current of a high voltage level. As an example, during the initialization for memory programming, a high stage charge pump with 100 .mu.A current may be needed to quickly step up the 10 VDC within a reasonable time.
Although after the initialization a low stage charge pump providing 5 VDC with 1 mA and a high stage charge pump providing 10 VDC with 100 nA are sufficient to sustain the programming, a high stage charge pump having very large circuit area has to be built in order to provide enough current for the initialization.